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CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
The CY7C1011CV33 is a high performance CMOS static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the "Truth Table" on page 9 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Temperature ranges Industrial: -40C to 85C Automotive-A: -40C to 85C Automotive-E: -40C to 125C Pin and function compatible with CY7C1011BV33 High speed tAA = 10 ns (Industrial and Automotive-A) tAA = 12 ns (Automotive-E) Low active power 360 mW (max) (Industrial and Automotive-A) Data Retention at 2.0 Automatic power down when deselected Independent control of upper and lower bits Easy memory expansion with CE and OE features Available in Pb-free 44-pin TSOP II, 44-pin TQFP and non Pb-free 48-Ball VFBGA packages

Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE
A10 A11
A12
A14
A15
Cypress Semiconductor Corporation Document Number: 38-05232 Rev. *H
*
198 Champion Court
A13
A16
A9
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 23, 2009
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CY7C1011CV33
Pin Configuration
Figure 1. 44-Pin TSOP II [1] Figure 2. 48-Ball VFBGA Pinout [1]
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1 BLE I/O8 I/O9
2 OE BHE I/O10
3 A0 A3 A5 NC NC
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
VSS I/O11 VCC I/O12
I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9
Figure 3. 44-Pin TQFP
BHE 35 BLE 34 33 32 31 30 29 28 27 26 25 24 23 21 12 13 14 16 17 18 15 19 20 22 A13
A14
A15
A11
A12
A16
A10 38
1 44 43 42 40 39 37 41 36 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 11 I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC
WE A0
A1
OE A6
A9
NC
A2
A5
A3
Note 1. NC pins are not connected on the die.
Document Number: 38-05232 Rev. *H
A4
A7
A8
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CY7C1011CV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Industrial Automotive-A Automotive-E Maximum CMOS Standby Current Industrial Automotive-A Automotive-E 10 10 15 -10 10 100 100 120 10 -12 12 95 Unit ns mA mA mA mA mA mA
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND[2] .....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2] ...................................... -0.5V to VCC+0.5V DC Input Voltage[2] .................................. -0.5V to VCC+0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Industrial Automotive-A Automotive -E Ambient Temperature (TA) -40C to +85C -40C to +85C -40C to +125C VCC 3.3V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current GND < VI < VCC Industrial Automotive-A Automotive -E IOZ GND < VI < VCC, Output disabled Industrial Automotive-A Automotive -E ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power Down Current --TTL Inputs Automatic CE Power Down Current -- CMOS Inputs Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Industrial Automotive-A Automotive -E ISB1 Industrial Automotive-A Automotive -E ISB2 Industrial Automotive-A Automotive -E 10 10 15 40 40 45 10 mA 100 100 120 40 mA -1 -1 +1 +1 -20 +20 95 mA Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 -20 -1 +20 +1 A 2.0 -0.3 -1 Max 2.4 0.4 VCC + 0.3 0.8 +1 -12 Min Max Unit V V V V A
Note 2. VIL (min) = -2.0V for pulse durations of less than 20 ns.
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board TSOP II 44.56 10.75 Figure 4. AC Test Loads and Waveforms [3]
10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12-ns devices: 3.3V OUTPUT R 317
TQFP 42.66 14.64
VFBGA 46.98 9.63
Unit C/W C/W
JA JC
Z = 50
30 pF*
30 pF*
R2 351
(a)
(b)
High-Z characteristics: 3.0V GND
Rise Time: 1 V/ns
ALL INPUT PULSES 90% 10% 90% 10%
3.3V OUTPUT 5 pF
R 317
R2 351
(c)
Fall Time: 1 V/ns
(d)
Note 3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown in Figure 4 (b). High-Z characteristics are tested for all speeds using the test load shown in Figure 4 (d).
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Switching Characteristics
Over the Operating Range [4] Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[6] Z[6] Z[6, 7] 0 10 Industrial/Automotive-A Automotive-E Byte Enable to Low Z Byte Disable to High Z Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[6] Z[6, 7] 7 10 7 7 0 0 7 5 0 3 5 8 0 5 12 8 8 0 0 8 6 0 3 6 0 6 5 Industrial/Automotive-A Automotive-E 0 5 3 5 0 12 6 8 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 6 0 6 OE HIGH to High Z[6, 7] CE HIGH to High 3 10 5 1 10 10 3 12 6 8 ns ns ns ns ns ns ns 1 12 12 s ns ns ns ns ns Description -10 Min Max Min -12 Max Unit
CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid
Write Cycle[8, 9]
Byte Enable to End of Write
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of "AC Test Loads and Waveforms [3]" on page 5. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
ICC ISB
Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Switching Waveforms
(continued) Figure 7. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATA IO tHD
Figure 8. Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes 13. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Switching Waveforms
(continued) Figure 9. Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA I/O
tSD
tHD
tLZWE
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0- I/O7 I/O8 - I/O15 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power Down Read - All Bits Read - Lower Bits Only Read - Upper Bits Only Write - All Bits Write - Lower Bits Only Write - Upper Bits Only Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Ordering Information
Speed (ns) 10 12 Ordering Code CY7C1011CV33-10BVI CY7C1011CV33-10ZSXA CY7C1011CV33-12AXI CY7C1011CV33-12ZSXE Package Diagram Package Type Operating Range Industrial Automotive-A Industrial Automotive-E 51-85150 48-ball (6 x 8 x 1 mm) VFBGA 51-85087 44-pin TSOP II (Pb-Free) 51-85064 44-pin TQFP (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free)
Package Diagrams
Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Package Diagrams
(continued) Figure 11. 44-Pin Thin Plastic Quad Flat Pack, 51-85064
12.000.25 SQ 10.000.10 SQ
44 34
0 MIN.
1 33
0.370.05 STAND-OFF 0.05 MIN. 0.15 MAX.
R. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE
R. 0.08 MIN. 0.20 MIN. 0.20 MIN.
0-7 0.600.15
1.00 REF.
11 23
0.80 B.S.C. DETAIL
A
12
22
NOTE: 1. JEDEC STD REF MS-026
SEATING PLANE 1.60 MAX. 121 (8X)
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
1.400.05 0.10 0.20 MAX.
SEE DETAIL
A
51-85064-*C
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Package Diagrams
(continued) Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
SEATING PLANE 0.26 MAX. C 1.00 MAX
51-85150-*D
Document Number: 38-05232 Rev. *H
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CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM Document Number: 38-05232 Issue Orig. of REV. ECN NO. Description of Change Date Change ** 117132 07/31/02 HGK New Data Sheet *A 118057 08/19/02 HGK Pin configuration for 48-ball FBGA correction *B 119702 10/11/02 DFP Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1 from 8 to 10 mA *C 386106 See ECN PCI Added lead-free parts in Ordering Information Table *D 498501 See ECN NXR Corrected typo in the Logic Block Diagram on page# 1 Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on page# 3 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table *E 522620 See ECN VKN Added Thermal Resistance Table *F 1891366 See ECN VKN/AESA Added -10ZSXA part Updated Ordering Information table *G 2428606 See ECN VKN/PYRS Corrected typo in the 44-Pin TSOP and 48-Ball FBGA pinout Removed Commercial parts Removed 15 ns speed bin Removed inactive parts from the Ordering Information table *H 2664421 02/25/09 VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05232 Rev. *H
Revised February 23, 2009
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